So… what’s wrong about my characterisation of computer hardware? Do you have any issue with the claim that RAM doesn’t talk directly to the SSD, but via the CPU? If yes, please show me the traces on the motherboard which enable that. About the importance of latency to CPU-type comremovedtions?
Or do you want to tell me how it’s absolutely unsuspicious to bang out a press release in tech and talk about “speed”, not distinguishing between bandwidth and latency? Where’s the fucking numbers. There’s no judging the tech without numbers and them not being forward with those numbers means they’re talking to investors, not techies.
I’m not even sure where you got this RAM talking to storage thing from. This is why I’m saying you don’t know what you’re talking about it. I think your fundamental understanding of this is flawed.
It was you who was talking about “bus paths” and “traversing CPU>RAM>SSD”. There’s neither buses connected up to any of those things nor does the data ever flow like that, it always flows via the CPU.
That’s three devices. There’s two connections between them, and they go “RAM<->CPU<->SSD”. The first <-> is the DRAM Phy, the second <-> is 1-4 PCIe lanes. Neither of them are a bus. There is no third connection.
So… what’s wrong about my characterisation of computer hardware? Do you have any issue with the claim that RAM doesn’t talk directly to the SSD, but via the CPU? If yes, please show me the traces on the motherboard which enable that. About the importance of latency to CPU-type comremovedtions?
Or do you want to tell me how it’s absolutely unsuspicious to bang out a press release in tech and talk about “speed”, not distinguishing between bandwidth and latency? Where’s the fucking numbers. There’s no judging the tech without numbers and them not being forward with those numbers means they’re talking to investors, not techies.
I’m not even sure where you got this RAM talking to storage thing from. This is why I’m saying you don’t know what you’re talking about it. I think your fundamental understanding of this is flawed.
It was you who was talking about “bus paths” and “traversing CPU>RAM>SSD”. There’s neither buses connected up to any of those things nor does the data ever flow like that, it always flows via the CPU.
🤣 That isn’t a relational diagram. Simply pointing out the three bus paths.
That’s three devices. There’s two connections between them, and they go “RAM<->CPU<->SSD”. The first <-> is the DRAM Phy, the second <-> is 1-4 PCIe lanes. Neither of them are a bus. There is no third connection.